1. Field of the Invention
The present invention relates to a manufacturing method with low thermal budget used for stacking different material layers on a substrate, and more particularly, to a self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane.
2. Description of the Prior Art
Silicon is currently a conventional semiconductor material, which is now widely used for CMOS devices and becomes an indispensable material for Integrated Circuits (ICs). However, silicon still can not be broadly applied to optoelectronic and high-frequency communications due to the limitation on its electron mobility (1350 cm2/V-S), hole mobility (480 cm2/V-S) and energy gap (1.12 eV). On the contrary, germanium (Ge) has higher electron mobility (˜3900 cm2/V-S) and hole mobility (˜1900 cm2/V-S) as well as lower energy gap (0.67 eV), therefore research and academic institutions all commit to the researches of germanium materials in optoelectronic and high-frequency electronic devices.
Recently, epitaxial films of Silicon-germanium (SiGe) become a popular material structure, and furthermore, the so-called hetero-junction semiconductor devices formed by monocrystalline silicon-germanium (Si1-xGex) on silicon substrate are gradually replacing the amorphous silicon optoelectronics, CMOS gate and thermal radiation sensors. However, it is well-known that the lattice constants of pure silicon material and pure germanium material are 5.43 Å and 5.65 Å, respectively. So that, a lattice mismatch of 4.2% would generate misfit dislocation defects between silicon and germanium when growing Si1-xGex epitaxial film on a silicon substrate; therefore, forming the Si1-xGex epitaxial film on the silicon substrate becomes difficult.
For growing Si1-xGex epitaxial film on silicon substrate, R.O.C. patent of TW I358755 teaches a method for manufacturing a semiconductor heterostructure. Please refer to FIG. 1, which illustrates a schematic process flow of the semiconductor heterostructure manufacturing method. As shown in FIG. 1, the method firstly grows a buffer layer 3′ of Si1-xGex on a Si substrate 2′ by epitaxy, wherein the concentration of Si/Ge in the buffer layer 3′ is changed according to the thickness of the buffer layer 3′, so as to make the lattice constant of the buffer layer 3′ be slowly changed. Next, a smooth layer 5′ having constant Si/Ge concentration is grown on the buffer layer 3′, and subsequently, a top layer 6′ of strain silicon is deposited on the smooth layer 5′; Then, a donor wafer 12′ is completed. Thus, according to the above-mentioned semiconductor heterostructure manufacturing method proposed by TW I358755, it is able to know that the Si1-xGex epitaxial film can be easily grown on silicon substrate through the assist of the buffer layer and the strain silicon layer.
Besides the semiconductor heterostructure manufacturing method taught by TW I358755, many research and academic institutions also propose some technologies for manufacturing semiconductor heterostructure; However, in summary, the conventional semiconductor heterostructure manufacturing methods still include the shortcoming and drawbacks as follows:
1. Whatever Ultra-high Vacuum Chemical Vapor Deposition (HV/CVD), Rapid-Thermal Chemical Vapor Deposition (RTCVD), Rapid-Thermal Chemical Vapor Deposition (RTCVD), or Metal-organic Chemical Vapor Deposition (MOCVD), the high temperature of 600° C.˜1000° C. in process lead to high thermal budget in manufacturing and integrating other electronic devices.2. Although the lattice mismatch issue can be solved by using the buffer layer in the conventional semiconductor heterostructure manufacturing method, not all of the heterogeneous materials have a suitable buffer layer for allowing it to be grown on Si substrate; in addition, because the buffer layer is full of lattice defects, which are against to vertical integration of devices. Although some semiconductor fabricator use direct wafer bonding way to solve above-mentioned issue, the wafer alignment between a donor wafer and the device wafer and how to remove the substrate become new issues. Moreover, the yield of the wafer bonding process always relies on the high request on the surface flatness of wafers.3. Moreover, the most important is that, the above-mentioned technology for manufacturing semiconductor heterostructure is not applicable to laterally join a SiGe epitaxial film to a silicon structural layer at the same planar level.
Accordingly, in view of the conventional semiconductor heterostructure manufacturing method still have shortcomings and drawbacks, the inventor of the present application has made great efforts to make inventive research thereon and eventually provided a self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane.